In sub-micron Complimentary Metal-Oxide Semiconductor (CMOS) manufacturing, disposable dielectric spacers are sometimes used to define the heavily doped contact region of a source/drain structure. In conventional processes that use disposable dielectric spacers, a first implant is performed prior to forming the first spacer. This first implant forms lightly-doped drain (LDD) regions. The L-shaped permanent spacer and the disposable spacer are then formed, with the disposable spacer overlying the L-shaped spacer. A second implant process is then performed so as to form the heavily doped contact region. The disposable spacer is then removed, leaving the L-shaped spacer. This process works well when there is sufficient space between adjacent gate structures. However, in applications where the spacing between adjacent gate structures is less than 0.2 microns, the vertical or nearly-vertical slope of the L-shaped spacer causes voids to form during deposition of the pre-metal dielectric layer. These voids in the pre-metal dielectric layer can lead to bridging defects in the subsequently formed contacts. In addition, the width of conventional L-shaped spacers takes up valuable space on the semiconductor surface, limiting size reduction of closely-spaced CMOS structures.
Accordingly there is a need for a process for forming a CMOS device that gives good gap-fill characteristics between adjacent gate structures. Also, there is a need for CMOS devices that do not have bridging defects. The present invention meets the above needs.